//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_8259A_H__
#define __ELASTOS_8259A_H__

#define MASTER_PIC(port)        (0x20 + (port))

#define SLAVE_PIC(port)         (0xa0 + (port))

#define SLAVE_IRQ               2

enum {
    ICW1_Port               = 0,
    ICW2_Port               = 1,
    ICW3_Port               = 1,
    ICW4_Port               = 1,
    OCW1_Port               = 1,
    OCW2_Port               = 0,
    OCW3_Port               = 0,
};

// Initialization Command Words 1 (ICW1)

#define ICW1                    __8BIT(4)

// If LTIM = 1, then the 8259A will operate in the level interrupt mode.
#define ICW1_LTIM               __8BIT(3)

// ADI: CALL address interval. ADI = 1 then interval = 4;
// ADI = 0 then interval = 8.
#define ICW1_ADI                __8BIT(2)

// SNGL: Single. Means that this is the only 8259A inthe system.
// If SNGL = 1 no ICW3 will be issued.
#define ICW_SNGL                __8BIT(1)

// IC4: If this bit is set-ICW4 has to be read.
// If ICW4 is not needed, set IC4 = 0.
#define ICW1_IC4                __8BIT(0)

// Initialization Command Words 2

// Initialization Command Words 3

#define ICW3_MASTER_IR          __8BIT(SLAVE_IRQ)

#define ICW3_SLAVE_ID           SLAVE_IRQ

// Initialization Command Words 3

// SFNM: If SFNM = 1 the special fully nested mode is programmed.
#define ICW4_SFNM               __8BIT(4)

// BUF: If BUF = 1 the buffered mode is programmed. In buffered mode
// SP/EN becomes an enable output and the master/slave determination is by M/S.
#define ICW4_BUF                __8BIT(3)

// If buffered mode is selected: M/S = 1 means the 8259A is programmed to be a
// master, M/S e 0 means the 8259A is programmed to be a slave.
// If BUF e 0, M/S has no function.
#define ICW4_MS                 __8BIT(2)

// AEOI: If AEOI e 1 the automatic end of interrupt mode is programmed.
#define ICW4_AEOI               __8BIT(1)

// uPM: Microprocessor mode: uPM = 0 sets the 8259A for MCS-80,
// 85 system operation, uPM e 1 sets the 8259A for 8086 system operation.
#define ICW4_uPM                __8BIT(0)

// Operation Command Words 1

// Operation Command Words 2

// R, SL, EOI-These three bits control the Rotate and End of Interrupt modes
// and combinations of the two.
// 001 -- non specific eoi command               |->  end of interrupt
// 011 -- specific eoi command                  -+
//
// 101 -- rotate on non specific eoi command    -+
// 100 -- rotate on automatic eoi mode(set)      |->  automatic rotation
// 000 -- rotate on automatic eoi mode(clear)   -+
//
// 111 -- rotate on specific eoi command         |->  specific rotation
// 110 -- set priority command                  -+
//
// 010 -- no operation
#define OCW2_R                  __8BIT(7)
#define OCW2_SL                 __8BIT(6)
#define OCW2_EOI                __8BIT(5)

// L2, L1, L0-These bits determine the interrupt level acted upon
// when the SL bit is active.
#define OCW2_L2                 __8BIT(2)
#define OCW2_L1                 __8BIT(1)
#define OCW2_L0                 __8BIT(0)

// Operation Control Word 3 (OCW3)

// ESMM-Enable Special Mask Mode. When this bit is set to 1 it enables
// the SMM bit to set or reset the Special Mask Mode.
// When ESMM = 0 the SMM bit becomes a ``don't care''.
#define OCW3_ESMM               __8BIT(6)

// SMM-Special Mask Mode. If ESMM = 1 and SMM = 1 the 8259A will enter Special
// Mask Mode. If ESMM = 1 and SMM = 0 the 8259A will revert to normal mask mode.
// When ESMM = 0, SMM has no effect.
#define OCW3_SMM                __8BIT(5)

#define OCW3                    __8BIT(3)

// 1 = poll command, 0 = no poll command
#define OCW3_P                  __8BIT(2)

// RR, RIS
// 00, 01 -- no action
// 10 -- read IR reg no next RD pulse
// 11 -- read IS reg no next RD pulse
#define OCW3_RR                 __8BIT(1)
#define OCW3_RIS                __8BIT(0)

#endif // __ELASTOS_8259A_H__
